In the manufacture of integrated circuits, interconnects may be formed on a semiconductor substrate using a copper damascene process. Such a process typically begins with a trench and/or via being etched into an insulator layer and then filled with copper metal to form the interconnect. It is often desirable to stack multiple layers to form an integrated circuit, by adding additional layers of insulator and metal-filled features. In such cases, various interconnect features can be used to electrically connect one layer to another, as desired for a given integrated circuit design. However, as device dimensions continue to scale down, the various interconnect features become narrower and closer together giving rise to a number of non-trivial problems.
As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the disclosure to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of a structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. In short, the figures are provided merely to show example structures.